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// include/hw/pci-host/designware.h

struct DesignwarePCIEHost {
    PCIHostState parent_obj;

    DesignwarePCIERoot root;

    struct {
        AddressSpace address_space;
        MemoryRegion address_space_root;

        MemoryRegion memory;
        MemoryRegion io;

        qemu_irq     irqs[4];
    } pci;

    MemoryRegion mmio;
};

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// include/hw/pci-host/designware.h

struct DesignwarePCIERoot {
    PCIBridge parent_obj;

    uint32_t atu_viewport;

#define DESIGNWARE_PCIE_VIEWPORT_OUTBOUND    0
#define DESIGNWARE_PCIE_VIEWPORT_INBOUND     1
#define DESIGNWARE_PCIE_NUM_VIEWPORTS        4

    DesignwarePCIEViewport viewports[2][DESIGNWARE_PCIE_NUM_VIEWPORTS];
    DesignwarePCIEMSI msi;
};

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// hw/pci-host/designware.c

static void designware_pcie_host_realize(DeviceState *dev, Error **errp)
{
    PCIHostState *pci = PCI_HOST_BRIDGE(dev);
    DesignwarePCIEHost *s = DESIGNWARE_PCIE_HOST(dev);
    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
    size_t i;

    ...

    memory_region_init(&s->pci.io, OBJECT(s), "pcie-pio", 16);

    // Initialize PCIe root sub-container MemoryRegion.
    memory_region_init(&s->pci.memory, OBJECT(s),
                       "pcie-bus-memory",
                       UINT64_MAX);

    // Create and assign DesignwarePCIEHost => PCIHostState->PCIBus
    // PCIBus' parent (DeviceState) is DesignwarePCIEHost.
    // pci.memory is the MemoryRegion for PCIe address space.
    // pci.io is the I/O MemoryRegion for PCIe address space.
    pci->bus = pci_register_root_bus(dev, "pcie",
                                     designware_pcie_set_irq,
                                     pci_swizzle_map_irq_fn,
                                     s,
                                     &s->pci.memory,
                                     &s->pci.io,
                                     0, 4,
                                     TYPE_PCIE_BUS);

    ....

    // Initialize PCIe root container MemoryRegion.
    memory_region_init(&s->pci.address_space_root,
                       OBJECT(s),
                       "pcie-bus-address-space-root",
                       UINT64_MAX);
    // Add pcie.memory as the subregion of PCIe root container MemoryRegion.
    memory_region_add_subregion(&s->pci.address_space_root,
                                0x0, &s->pci.memory);
    // Initialize PCIe root address space with root container MemoryRegion.
    address_space_init(&s->pci.address_space,
                       &s->pci.address_space_root,
                       "pcie-bus-address-space");
    // Specify pci.address_space as the address space of
    pci_setup_iommu(pci->bus, designware_pcie_host_set_iommu, s);

    // Set DesignwarePCIERoot's parent_bus to:
    // DesignwarePCIEHost => PCIHostState->PCIBus.
    qdev_realize(DEVICE(&s->root), BUS(pci->bus), &error_fatal);
}

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// hw/pci-host/designware.c

static AddressSpace *designware_pcie_host_set_iommu(PCIBus *bus, void *opaque,
                                                    int devfn)
{
    DesignwarePCIEHost *s = DESIGNWARE_PCIE_HOST(opaque);

    return &s->pci.address_space;
}

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// hw/pci/pci.c

// DesignwarePCIERoot is a PCIDevice.
static void pci_qdev_realize(DeviceState *qdev, Error **errp)
{
    PCIDevice *pci_dev = (PCIDevice *)qdev;
    PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
    ObjectClass *klass = OBJECT_CLASS(pc);
    Error *local_err = NULL;
    bool is_default_rom;
    uint16_t class_id;

    ...

    // Add DesignwarePCIERoot to DesignwarePCIEHost => PCIHostState->PCIBus's
    // device list.
    pci_dev = do_pci_register_device(pci_dev,
                                     object_get_typename(OBJECT(qdev)),
                                     pci_dev->devfn, errp);
    if (pci_dev == NULL)
        return;

    // This will call designware_pcie_root_realize().
    if (pc->realize) {
        pc->realize(pci_dev, &local_err);
        if (local_err) {
            error_propagate(errp, local_err);
            do_pci_unregister_device(pci_dev);
            return;
        }
    }

      ...
}

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// hw/pci/pci.c

/* -1 for devfn means auto assign */
static PCIDevice *do_pci_register_device(PCIDevice *pci_dev,
                                         const char *name, int devfn,
                                         Error **errp)
{
    PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
    PCIConfigReadFunc *config_read = pc->config_read;
    PCIConfigWriteFunc *config_write = pc->config_write;
    Error *local_err = NULL;
    DeviceState *dev = DEVICE(pci_dev);
    PCIBus *bus = pci_get_bus(pci_dev);

    ...

    pci_dev->devfn = devfn;
    pci_dev->requester_id_cache = pci_req_id_cache_get(pci_dev);
    pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);

    memory_region_init(&pci_dev->bus_master_container_region, OBJECT(pci_dev),
                       "bus master container", UINT64_MAX);
    address_space_init(&pci_dev->bus_master_as,
                       &pci_dev->bus_master_container_region, pci_dev->name);

    ...

    if (!config_read)
        config_read = pci_default_read_config;
    if (!config_write)
        config_write = pci_default_write_config;
    pci_dev->config_read = config_read;
    pci_dev->config_write = config_write;
    // Add this PCIDevice to its parent bus's (PCIBus) device list.
    bus->devices[devfn] = pci_dev;
    pci_dev->version_id = 2; /* Current pci device vmstate version */
    return pci_dev;
}

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// hw/pci-host/designware.c

static DesignwarePCIEHost *
designware_pcie_root_to_host(DesignwarePCIERoot *root)
{
    // DesignwarePCIEHost => PCIHostState->PCIBus
    BusState *bus = qdev_get_parent_bus(DEVICE(root));
    // PCIBus' parent (DeviceState) is DesignwarePCIEHost
    return DESIGNWARE_PCIE_HOST(bus->parent);
}

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// hw/pci-host/designware.c

static void designware_pcie_root_realize(PCIDevice *dev, Error **errp)
{
    DesignwarePCIERoot *root = DESIGNWARE_PCIE_ROOT(dev);
    DesignwarePCIEHost *host = designware_pcie_root_to_host(root);
    MemoryRegion *address_space = &host->pci.memory;
    PCIBridge *br = PCI_BRIDGE(dev);
    DesignwarePCIEViewport *viewport;
    /*
     * Dummy values used for initial configuration of MemoryRegions
     * that belong to a given viewport
     */
    const hwaddr dummy_offset = 0;
    const uint64_t dummy_size = 4;
    size_t i;

    br->bus_name  = "dw-pcie";

    ...

    pci_bridge_initfn(dev, TYPE_PCIE_BUS);

    ...
}

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// include/hw/pci/pci_bridge.h

struct PCIBridge {
    /*< private >*/
    PCIDevice parent_obj;
    /*< public >*/

    /* private member */
    PCIBus sec_bus;
    /*
     * Memory regions for the bridge's address spaces.  These regions are not
     * directly added to system_memory/system_io or its descendants.
     * Bridge's secondary bus points to these, so that devices
     * under the bridge see these regions as its address spaces.
     * The regions are as large as the entire address space -
     * they don't take into account any windows.
     */
    MemoryRegion address_space_mem;
    MemoryRegion address_space_io;

    PCIBridgeWindows *windows;

    pci_map_irq_fn map_irq;
    const char *bus_name;
};

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// hw/pci/pci_bridge.c

void pci_bridge_initfn(PCIDevice *dev, const char *typename)
{
    // dev is DesignwarePCIERoot

    // DesignwarePCIERoot's parent_bus is:
    // DesignwarePCIEHost => PCIHostState->PCIBus.
    PCIBus *parent = pci_get_bus(dev);
    PCIBridge *br = PCI_BRIDGE(dev);
    PCIBus *sec_bus = &br->sec_bus;

    ...

    /*
     * If we don't specify the name, the bus will be addressed as <id>.0, where
     * id is the device id.
     * Since PCI Bridge devices have a single bus each, we don't need the index:
     * let users address the bus using the device name.
     */
    if (!br->bus_name && dev->qdev.id && *dev->qdev.id) {
            br->bus_name = dev->qdev.id;
    }

    // Initialize sec_bus.
    qbus_init(sec_bus, sizeof(br->sec_bus), typename, DEVICE(dev),
              br->bus_name);
    // sec_bus's parent_dev (PCIDevice) is DesignwarePCIERoot.
    sec_bus->parent_dev = dev;
    sec_bus->map_irq = br->map_irq ? br->map_irq : pci_swizzle_map_irq_fn;
    sec_bus->address_space_mem = &br->address_space_mem;
    memory_region_init(&br->address_space_mem, OBJECT(br), "pci_bridge_pci", UINT64_MAX);
    sec_bus->address_space_io = &br->address_space_io;
    memory_region_init(&br->address_space_io, OBJECT(br), "pci_bridge_io",
                       4 * GiB);
    br->windows = pci_bridge_region_init(br);
    QLIST_INIT(&sec_bus->child);
    // Add sec_bus to DesignwarePCIEHost => PCIHostState->PCIBus's child list.
    QLIST_INSERT_HEAD(&parent->child, sec_bus, sibling);
}

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        +--------------------------+    +--------------------------------------------------------------------------------------------------------+
        |                          |    |                                                                                                        |
        |    DesignwarePCIEHost    | <--+                                                                                                        |
        |                          |        +----------------------+   +-------------------------------------------------------------------------|----+
        +--------------------------+        |                      |   |                                                                         |    |
        | PCIHostState parent_obj; | =====> |     PCIHostState     |   |                                                                         |    |
        +--------------------------+        |                      |   |                                                                         |    |
   +--> | DesignwarePCIERoot root; | ===+   +----------------------+   |                                                                         |    |
   |    +--------------------------+    |   | SysBusDevice busdev; |   |    +------------------------------+                                     |    |
   |                                    |   +----------------------+   |    |                              |                                     |    |
   |                                    |   | PCIBus *bus;         | ==|==> |            PCIBus            |                                     |    |
   |                                    |   | ("pcie")             |   |    |                              |        +----------------------+     |    |
   |                                    |   +----------------------+   |    +------------------------------+        |                      |     |    |
   |                                    |               ^              |    | BusState qbus;               | =====> |       BusState       |     |    |
   |                                    v               |              |    +------------------------------+        |                      |     |    |
   |                        +-----------------------+   +--------------+    | PCIDevice *parent_dev;       |        +----------------------+     |    |
   |                        |                       |                       +------------------------------+        | Object obj;          |     |    |
   |                        |   DesignwarePCIERoot  |                       | QLIST_HEAD(, PCIBus) child;  | <--+   +----------------------+     |    |
   |                        |                       |                       +------------------------------+    |   | DeviceState *parent; | ----+    |
   |                        +-----------------------+                       | QLIST_ENTRY(PCIBus) sibling; |    |   +----------------------+          |
   |                        | PCIBridge parent_obj; | =============+        +------------------------------+    |                                     |
   |                        +-----------------------+              |                                            |                                     |
   |                                                               |                                            |                                     |
   |                                                               v                                            |                                     |
   |                                                   +-----------------------+                                |                                     |
   |                                                   |                       |   +----------------------------+                                     |
   |                                                   |       PCIBridge       |   |                                                                  |
   |                                                   |                       |   |    +-------------------+                                         |
   |                                                   +-----------------------+   |    |                   |                                         |
   |           +------------------------------+        | PCIDevice parent_obj; | ==|==> |     PCIDevice     |                                         |
   |           |                              |        +-----------------------+   |    |                   |        +-----------------------+        |
   |           |            PCIBus            | <===== | PCIBus sec_bus;       |   |    +-------------------+        |                       |        |
   |           |                              |        | ("dw-pcie")           |   |    | DeviceState qdev; | =====> |      DeviceState      |        |
   |           +------------------------------+        +-----------------------+   |    +-------------------+        |                       |        |
   |           | BusState qbus;               |                    |               |                                 +-----------------------+        |
   |           +------------------------------+                Added to            |                                 | Object parent_obj;    |        |
   +---------- | PCIDevice *parent_dev;       |                    |               |                                 +-----------------------+        |
               +------------------------------+                    +---------------+                                 | BusState *parent_bus; | -------+
               | QLIST_HEAD(, PCIBus) child;  |                                                                      +-----------------------+
               +------------------------------+
               | QLIST_ENTRY(PCIBus) sibling; |
               +------------------------------+

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// hw/pci-host/designware.c

static void designware_pcie_host_realize(DeviceState *dev, Error **errp)
{
    ...

    memory_region_init_io(&s->mmio,
                          OBJECT(s),
                          &designware_pci_mmio_ops,
                          s,
                          "pcie.reg", 4 * 1024);
    sysbus_init_mmio(sbd, &s->mmio);

    ...
}

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// hw/pci-host/designware.c

static const MemoryRegionOps designware_pci_mmio_ops = {
    .read       = designware_pcie_host_mmio_read,
    .write      = designware_pcie_host_mmio_write,
    .endianness = DEVICE_LITTLE_ENDIAN,

        ...
    },
};

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// hw/pci-host/designware.c

static uint64_t designware_pcie_host_mmio_read(void *opaque, hwaddr addr,
                                               unsigned int size)
{
    PCIHostState *pci = PCI_HOST_BRIDGE(opaque);
    // Write to DesignwarePCIEHost will issue the PCIe config read
    // request to DesignwarePCIERoot.
    // device => DesignwarePCIERoot.
    PCIDevice *device = pci_find_device(pci->bus, 0, 0);

    return pci_host_config_read_common(device,
                                       addr,
                                       pci_config_size(device),
                                       size);
}

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// hw/pci-host/designware.c

static void designware_pcie_host_mmio_write(void *opaque, hwaddr addr,
                                            uint64_t val, unsigned int size)
{
    PCIHostState *pci = PCI_HOST_BRIDGE(opaque);
    // Read from DesignwarePCIEHost will issue the PCIe config read
    // request to DesignwarePCIERoot.
    // device => DesignwarePCIERoot.
    PCIDevice *device = pci_find_device(pci->bus, 0, 0);

    return pci_host_config_write_common(device,
                                        addr,
                                        pci_config_size(device),
                                        val, size);
}

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// hw/pci-host/designware.c

static void designware_pcie_root_class_init(ObjectClass *klass, void *data)
{
    ...

    k->config_read = designware_pcie_root_config_read;
    k->config_write = designware_pcie_root_config_write;

    ...
}

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// hw/pci-host/designware.c

static uint32_t
designware_pcie_root_config_read(PCIDevice *d, uint32_t address, int len)
{
    DesignwarePCIERoot *root = DESIGNWARE_PCIE_ROOT(d);
    DesignwarePCIEViewport *viewport =
        designware_pcie_root_get_current_viewport(root);

    uint32_t val;

    switch (address) {
    case DESIGNWARE_PCIE_PORT_LINK_CONTROL:
        /*
         * Linux guest uses this register only to configure number of
         * PCIE lane (which in our case is irrelevant) and doesn't
         * really care about the value it reads from this register
         */
        val = 0xDEADBEEF;
        break;

    ...

    case DESIGNWARE_PCIE_ATU_CR1:
    case DESIGNWARE_PCIE_ATU_CR2:
        val = viewport->cr[(address - DESIGNWARE_PCIE_ATU_CR1) /
                           sizeof(uint32_t)];
        break;

    default:
        val = pci_default_read_config(d, address, len);
        break;
    }

    return val;
}

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// hw/pci-host/designware.c

static void designware_pcie_root_config_write(PCIDevice *d, uint32_t address,
                                              uint32_t val, int len)
{
    DesignwarePCIERoot *root = DESIGNWARE_PCIE_ROOT(d);
    DesignwarePCIEHost *host = designware_pcie_root_to_host(root);
    DesignwarePCIEViewport *viewport =
        designware_pcie_root_get_current_viewport(root);

    switch (address) {
    case DESIGNWARE_PCIE_PORT_LINK_CONTROL:
    case DESIGNWARE_PCIE_LINK_WIDTH_SPEED_CONTROL:
    case DESIGNWARE_PCIE_PHY_DEBUG_R1:
        /* No-op */
        break;

      ...

    case DESIGNWARE_PCIE_ATU_CR1:
        viewport->cr[0] = val;
        break;
    case DESIGNWARE_PCIE_ATU_CR2:
        viewport->cr[1] = val;
        designware_pcie_update_viewport(root, viewport);
        break;

    default:
        pci_bridge_write_config(d, address, val, len);
        break;
    }
}

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// hw/pci-host/designware.c

static void designware_pcie_root_realize(PCIDevice *dev, Error **errp)
{
    DesignwarePCIERoot *root = DESIGNWARE_PCIE_ROOT(dev);
    DesignwarePCIEHost *host = designware_pcie_root_to_host(root);
    MemoryRegion *address_space = &host->pci.memory;
    PCIBridge *br = PCI_BRIDGE(dev);
    DesignwarePCIEViewport *viewport;

        ...

    for (i = 0; i < DESIGNWARE_PCIE_NUM_VIEWPORTS; i++) {
        MemoryRegion *source, *destination, *mem;
        const char *direction;
        char *name;

        viewport = &root->viewports[DESIGNWARE_PCIE_VIEWPORT_INBOUND][i];
        viewport->inbound = true;
        viewport->base    = 0x0000000000000000ULL;
        viewport->target  = 0x0000000000000000ULL;
        viewport->limit   = UINT32_MAX;
        viewport->cr[0]   = DESIGNWARE_PCIE_ATU_TYPE_MEM;

        source      = &host->pci.address_space_root;
        destination = get_system_memory();
        direction   = "Inbound";

        /*
         * Configure MemoryRegion implementing PCI -> CPU memory
         * access
         */
        // Assign ViewPort's MEM MemoryRegion as the alias of System memory
        // (destination).
        // The actual offset/size will be updated in
        // designware_pcie_update_viewport().
        mem  = &viewport->mem;
        name = designware_pcie_viewport_name(direction, i, "MEM");
        memory_region_init_alias(mem, OBJECT(root), name, destination,
                                 dummy_offset, dummy_size);
        // Add ViewPort's MEM MemoryRegion as the subregion of PCIe
        // Host Controller root memory (source).
        // => PCIe Host Controller root memory -> ViewPort MEM -> System memory.
        memory_region_add_subregion_overlap(source, dummy_offset, mem, -1);
        memory_region_set_enabled(mem, false);
        g_free(name);

        viewport = &root->viewports[DESIGNWARE_PCIE_VIEWPORT_OUTBOUND][i];
        viewport->root    = root;
        viewport->inbound = false;
        viewport->base    = 0x0000000000000000ULL;
        viewport->target  = 0x0000000000000000ULL;
        viewport->limit   = UINT32_MAX;
        viewport->cr[0]   = DESIGNWARE_PCIE_ATU_TYPE_MEM;

        destination = &host->pci.memory;
        direction   = "Outbound";
        source      = get_system_memory();

        /*
         * Configure MemoryRegion implementing CPU -> PCI memory
         * access
         */
        // Assign ViewPort's MEM MemoryRegion as the alias of PCIe Host
        // Controller root memory (destination).
        // The actual offset/size will be updated in
        // designware_pcie_update_viewport().
        mem  = &viewport->mem;
        name = designware_pcie_viewport_name(direction, i, "MEM");
        memory_region_init_alias(mem, OBJECT(root), name, destination,
                                 dummy_offset, dummy_size);
        // Add ViewPort's MEM MemoryRegion as the subregion of System memory
        // (source).
        // System memory -> ViewPort MEM -> PCIe Host Controller root memory.
        memory_region_add_subregion(source, dummy_offset, mem);
        memory_region_set_enabled(mem, false);
        g_free(name);

        /*
         * Configure MemoryRegion implementing access to configuration
         * space
         */
        mem  = &viewport->cfg;
        name = designware_pcie_viewport_name(direction, i, "CFG");
        memory_region_init_io(&viewport->cfg, OBJECT(root),
                              &designware_pci_host_conf_ops,
                              viewport, name, dummy_size);
        // Add ViewPort's CFG MemoryRegion as the subregion of System memory
        // (source).
        // System memory -> ViewPort CFG -> designware_pci_host_conf_ops().
        memory_region_add_subregion(source, dummy_offset, mem);
        memory_region_set_enabled(mem, false);
        g_free(name);
    }

    /*
     * If no inbound iATU windows are configured, HW defaults to
     * letting inbound TLPs to pass in. We emulate that by exlicitly
     * configuring first inbound window to cover all of target's
     * address space.
     *
     * NOTE: This will not work correctly for the case when first
     * configured inbound window is window 0
     */
    viewport = &root->viewports[DESIGNWARE_PCIE_VIEWPORT_INBOUND][0];
    viewport->cr[1] = DESIGNWARE_PCIE_ATU_ENABLE;
    designware_pcie_update_viewport(root, viewport);

    memory_region_init_io(&root->msi.iomem, OBJECT(root),
                          &designware_pci_host_msi_ops,
                          root, "pcie-msi", 0x4);
    /*
     * We initially place MSI interrupt I/O region a adress 0 and
     * disable it. It'll be later moved to correct offset and enabled
     * in designware_pcie_root_update_msi_mapping() as a part of
     * initialization done by guest OS
     */
    memory_region_add_subregion(address_space, dummy_offset, &root->msi.iomem);
    memory_region_set_enabled(&root->msi.iomem, false);
}

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// hw/pci-host/designware.c

static const MemoryRegionOps designware_pci_host_conf_ops = {
    .read = designware_pcie_root_data_read,
    .write = designware_pcie_root_data_write,
    .endianness = DEVICE_LITTLE_ENDIAN,
    .valid = {
        .min_access_size = 1,
        .max_access_size = 4,
    },
};

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// hw/pci-host/designware.c

static uint64_t designware_pcie_root_data_read(void *opaque, hwaddr addr,
                                               unsigned len)
{
    return designware_pcie_root_data_access(opaque, addr, NULL, len);
}

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// hw/pci-host/designware.c

static void designware_pcie_root_data_write(void *opaque, hwaddr addr,
                                            uint64_t val, unsigned len)
{
    designware_pcie_root_data_access(opaque, addr, &val, len);
}

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// hw/pci-host/designware.c

static uint64_t designware_pcie_root_data_access(void *opaque, hwaddr addr,
                                                 uint64_t *val, unsigned len)
{
    DesignwarePCIEViewport *viewport = opaque;
    DesignwarePCIERoot *root = viewport->root;

        // Config the PCIe devices (BDF) managed by PCIe Host Controller.
    const uint8_t busnum = DESIGNWARE_PCIE_ATU_BUS(viewport->target);
    const uint8_t devfn  = DESIGNWARE_PCIE_ATU_DEVFN(viewport->target);
    PCIBus    *pcibus    = pci_get_bus(PCI_DEVICE(root));
    PCIDevice *pcidev    = pci_find_device(pcibus, busnum, devfn);

    if (pcidev) {
        addr &= pci_config_size(pcidev) - 1;

        if (val) {
            pci_host_config_write_common(pcidev, addr,
                                         pci_config_size(pcidev),
                                         *val, len);
        } else {
            return pci_host_config_read_common(pcidev, addr,
                                               pci_config_size(pcidev),
                                               len);
        }
    }

    return UINT64_MAX;
}

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    dmpcie@1200000000 {
        compatible = "snps,dw-pcie";
        interrupt-map-mask = <0x00 0x00 0x00 0x07>;
        interrupt-map = <0x00 0x00 0x00 0x01 0x0f 0x10 0x04 0x00 0x00 0x00 0x02 0x0f 0x11 0x04 0x00 0x00 0x00 0x03 0x0f 0x12 0x04 0x00 0x00 0x00 0x04 0x0f 0x13 0x04>;
        interrupt-names = "inta", "intb", "intc", "msi";
        #interrupt-cells = <0x01>;
        interrupts = <0x0f 0x04 0x10 0x04 0x11 0x04 0x12 0x04 0x13 0x04>;
        interrupt-parent = <0x0f>;
        dma-ranges = <0x2000000 0x00 0x80000000 0x00 0x80000000 0x00 0x80000000>;
        ranges = <0x81000000 0x00 0x60080000 0x00 0x60080000 0x00 0x10000
            0x82000000 0x00 0x60090000 0x00 0x60090000 0x00 0xff70000
            0x82000000 0x00 0x70000000 0x00 0x70000000 0x00 0x10000000
            0xc3000000 0x20 0x00 0x20 0x00 0x01 0x00>;
        bus-range = <0x00 0xff>;
        num-lanes = <0x04>;
        dma-coherent;
        device_type = "pci";
        #size-cells = <0x02>;
        #address-cells = <0x03>;
        reg-names = "config", "dbi", "mgmt";
        reg = <0x12 0x00 0x00 0x10000000
               0x11 0x00 0x01 0x00
               0x00 0x20004000 0x00 0x1000>;
        interrupt-controller {
            interrupt-controller;
            #address-cell = <0x00>;
        };
    };